Apparatus and method for power management of memory circuits by a system or component thereof

ABSTRACT

An apparatus and method are provided for communicating with a plurality of physical memory circuits. In use, at least one virtual memory circuit is simulated where at least one aspect (e.g. power-related aspect, etc.) of such virtual memory circuit(s) is different from at least one aspect of at least one of the physical memory circuits. Further, in various embodiments, such simulation may be carried out by a system (or component thereof), an interface circuit, etc.

RELATED APPLICATION(S)

The present application is a continuation-in-part of an applicationentitled “SYSTEM AND METHOD FOR POWER MANAGEMENT IN MEMORY SYSTEMS AND”and filed Sep. 20, 2006 under attorney docket number MRM1P010_SMITH0019Uwhich, in turn, is a continuation-in-part of an application filed Jul.31, 2006 under application Ser. No. 11/461,439, which are eachincorporated herein by reference for all purposes. However, insofar asany definitions, information used for claim interpretation, etc. fromthe above parent applications conflict with that set forth herein, suchdefinitions, information, etc. in the present application should apply.

FIELD OF THE INVENTION

The present invention relates to memory, and more particularly to powermanagement in memory systems that contain multiple memory circuits.

BACKGROUND

The memory capacity requirements of various systems are increasingrapidly. However, other industry trends such as higher memory bus speedsand small form factor machines, etc. are reducing the number of memorymodule slots in such systems. Thus, a need exists in the industry forlarger capacity memory circuits to be used in such systems.

However, there is also a limit to the power that may be dissipated perunit volume in the space available to the memory circuits. As a result,large capacity memory modules may be limited in terms of power that thememory modules may dissipate, and/or limited in terms of the ability ofpower supply systems to deliver sufficient power to such memory modules.There is thus a need for overcoming these limitations and/or otherproblems associated with the prior art.

SUMMARY

An apparatus and method are provided for communicating with a pluralityof physical memory circuits. In use, at least one virtual memory circuitis simulated where at least one aspect (e.g. power-related aspect, etc.)of such virtual memory circuit(s) is different from at least one aspectof at least one of the physical memory circuits. Further, in variousembodiments, such simulation may be carried out by a system (orcomponent thereof), an interface circuit, etc.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a multiple memory circuit framework, in accordancewith one embodiment.

FIG. 2 shows an exemplary embodiment of an interface circuit including aregister and a buffer that is operable to interface memory circuits anda system.

FIG. 3 shows an alternative exemplary embodiment of an interface circuitincluding a register and a buffer that is operable to interface memorycircuits and a system.

FIG. 4 shows an exemplary embodiment of an interface circuit includingan advanced memory buffer (AMB) and a buffer that is operable tointerface memory circuits and a system.

FIG. 5 shows an exemplary embodiment of an interface circuit includingan AMB, a register, and a buffer that is operable to interface memorycircuits and a system.

FIG. 6 shows an alternative exemplary embodiment of an interface circuitincluding an AMB and a buffer that is operable to interface memorycircuits and a system.

FIG. 7 shows an exemplary embodiment of a plurality of physical memorycircuits that are mapped by a system, and optionally an interfacecircuit, to appear as a virtual memory circuit with one aspect that isdifferent from that of the physical memory circuits.

DETAILED DESCRIPTION

FIG. 1 illustrates a multiple memory circuit framework 100, inaccordance with one embodiment. As shown, included are an interfacecircuit 102, a plurality of memory circuits 104A, 104B, 104N, and asystem 106. In the context of the present description, such memorycircuits 104A, 104B, 104N may include any circuit capable of serving asmemory.

For example, in various embodiments, at least one of the memory circuits104A, 104B, 104N may include a monolithic memory circuit, asemiconductor die, a chip, a packaged memory circuit, or any other typeof tangible memory circuit. In one embodiment, the memory circuits 104A,104B, 104N may take the form of a dynamic random access memory (DRAM)circuit. Such DRAM may take any form including, but not limited to,synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM,DDR2 SDRAM, DDR3 SDRAM, etc.), graphics double data rate synchronousDRAM (GDDR SDRAM, GDDR2 SDRAM, GDDR3 SDRAM, etc.), quad data rate DRAM(QDR DRAM), RAMBUS XDR DRAM (SDR DRAM), fast page mode DRAM (FPM DRAM),video DRAM (VDRAM), extended data out DRAM (EDO DRAM), burst EDO RAM(BEDO DRAM), multibank DRAM (MDRAM), synchronous graphics RAM (SGRAM),and/or any other type of DRAM.

In another embodiment, at least one of the memory circuits 104A, 104B,104N may include magnetic random access memory (MRAM), intelligentrandom access memory (IRAM), distributed network architecture (DNA)memory, window random access memory (WRAM), flash memory (e.g. NAND,NOR, etc.), pseudostatic random access memory (PSRAM), Low-PowerSynchronous Dynamic Random Access Memory (LP-SDRAM), PolymerFerroelectric RAM (PFRAM), OVONICS Unified Memory (OUM) or otherchalcogenide memory, Phase-change Memory (PCM), Phase-change RandomAccess Memory (PRAM), Ferrolectric RAM (FeRAM), REsistance RAM (R-RAM orRRAM), wetware memory, memory based on semiconductor, atomic, molecular,optical, organic, biological, chemical, or nanoscale technology, and/orany other type of volatile or nonvolatile, random or non-random access,serial or parallel access memory circuit.

Strictly, as an option, the memory circuits 104A, 104B, 104N may or maynot be positioned on at least one dual in-line memory module (DIMM) (notshown). In various embodiments, the DIMM may include a registered DIMM(R-DIMM), a small outline-DIMM (SO-DIMM), a fully buffered DIMM(FB-DIMM), an unbuffered DIMM (UDIMM), single inline memory module(SIMM), a MiniDIMM, a very low profile (VLP) R-DIMM, etc. In otherembodiments, the memory circuits 104A, 104B, 104N may or may not bepositioned on any type of material forming a substrate, card, module,sheet, fabric, board, carrier or other any other type of solid orflexible entity, form, or object. Of course, in other embodiments, thememory circuits 104A, 104B, 104N may or may not be positioned in or onany desired entity, form, or object for packaging purposes. Still yet,the memory circuits 104A, 104B, 104N may or may not be organized, eitheras a group (or as groups) collectively, or individually, onto one ormore portions(s). In the context of the present description, the termportion(s) (e.g. of a memory circuit(s)) shall refer to any physical,logical or electrical arrangement(s), partition(s), subdivisions(s)(e.g. banks, sub-banks, ranks, sub-ranks, rows, columns, pages, etc.),or any other portion(s), for that matter.

Further, in the context of the present description, the system 106 mayinclude any system capable of requesting and/or initiating a processthat results in an access of the memory circuits 104A, 104B, 104N. As anoption, the system 106 may accomplish this utilizing a memory controller(not shown), or any other desired mechanism. In one embodiment, suchsystem 106 may include a system in the form of a desktop computer, alap-top computer, a server, a storage system, a networking system, aworkstation, a personal digital assistant (PDA), a mobile phone, atelevision, a computer peripheral (e.g. printer, etc.), a consumerelectronics system, a communication system, and/or any other softwareand/or hardware, for that matter.

The interface circuit 102 may, in the context of the presentdescription, refer to any circuit capable of communicating (e.g.interfacing, buffering, etc.) with the memory circuits 104A, 104B, 104Nand the system 106. For example, the interface circuit 102 may, in thecontext of different embodiments, include a circuit capable of directly(e.g. via wire, bus, connector, and/or any other direct communicationmedium, etc.) and/or indirectly (e.g. via wireless, optical, capacitive,electric field, magnetic field, electromagnetic field, and/or any otherindirect communication medium, etc.) communicating with the memorycircuits 104A, 104B, 104N and the system 106. In additional differentembodiments, the communication may use a direct connection (e.g.point-to-point, single-drop bus, multi-drop bus, serial bus, parallelbus, link, and/or any other direct connection, etc.) or may use anindirect connection (e.g. through intermediate circuits, intermediatelogic, an intermediate bus or busses, and/or any other indirectconnection, etc.).

In additional optional embodiments, the interface circuit 102 mayinclude one or more circuits, such as a buffer (e.g. buffer chip,multiplexer/de-multiplexer chip, synchronous multiplexer/de-multiplexerchip, etc.), register (e.g. register chip, data register chip,address/control register chip, etc.), advanced memory buffer (AMB) (e.g.AMB chip, etc.), a component positioned on at least one DIMM, etc.

In various embodiments and in the context of the present description, abuffer chip may be used to interface bidirectional data signals, and mayor may not use a clock to re-time or re-synchronize signals in a wellknown manner. A bidirectional signal is a well known use of a singleconnection to transmit data in two directions. A data register chip maybe a register chip that also interfaces bidirectional data signals. Amultiplexer/de-multiplexer chip is a well known circuit that mayinterface a first number of bidirectional signals to a second number ofbidirectional signals. A synchronous multiplexer/de-multiplexer chip mayadditionally use a clock to re-time or re-synchronize the first orsecond number of signals. In the context of the present description, aregister chip may be used to interface and optionally re-time orre-synchronize address and control signals. The term address/controlregister chip may be used to distinguish a register chip that onlyinterfaces address and control signals from a data register chip, whichmay also interface data signals.

Moreover, the register may, in various embodiments, include a JEDECSolid State Technology Association (known as JEDEC) standard register (aJEDEC register), a register with forwarding, storing, and/or bufferingcapabilities, etc. In various embodiments, the registers, buffers,and/or any other interface circuit(s) 102 may be intelligent, that is,include logic that are capable of one or more functions such asgathering and/or storing information; inferring, predicting, and/orstoring state and/or status; performing logical decisions; and/orperforming operations on input signals, etc. In still other embodiments,the interface circuit 102 may optionally be manufactured in monolithicform, packaged form, printed form, and/or any other manufactured form ofcircuit, for that matter.

In still yet another embodiment, a plurality of the aforementionedinterface circuits 102 may serve, in combination, to interface thememory circuits 104A, 104B, 104N and the system 106. Thus, in variousembodiments, one, two, three, four, or more interface circuits 102 maybe utilized for such interfacing purposes. In addition, multipleinterface circuits 102 may be relatively configured or connected in anydesired manner. For example, the interface circuits 102 may beconfigured or connected in parallel, serially, or in variouscombinations thereof. The multiple interface circuits 102 may use directconnections to each other, indirect connections to each other, or even acombination thereof. Furthermore, any number of the interface circuits102 may be allocated to any number of the memory circuits 104A, 104B,104N. In various other embodiments, each of the plurality of interfacecircuits 102 may be the same or different. Even still, the interfacecircuits 102 may share the same or similar interface tasks and/orperform different interface tasks.

While the memory circuits 104A, 104B, 104N, interface circuit 102, andsystem 106 are shown to be separate parts, it is contemplated that anyof such parts (or portion(s) thereof) may be integrated in any desiredmanner. In various embodiments, such optional integration may involvesimply packaging such parts together (e.g. stacking the parts to form astack of DRAM circuits, a DRAM stack, a plurality of DRAM stacks, ahardware stack, where a stack may refer to any bundle, collection, orgrouping of parts and/or circuits, etc.) and/or integrating themmonolithically. Just by way of example, in one optional embodiment, atleast one interface circuit 102 (or portion(s) thereof) may be packagedwith at least one of the memory circuits 104A, 104B, 104N. Thus, a DRAMstack may or may not include at least one interface circuit (orportion(s) thereof). In other embodiments, different numbers of theinterface circuit 102 (or portions(s) thereof) may be packaged together.Such different packaging arrangements, when employed, may optionallyimprove the utilization of a monolithic silicon implementation, forexample.

The interface circuit 102 may be capable of various functionality, inthe context of different embodiments. For example, in one optionalembodiment, the interface circuit 102 may interface a plurality ofsignals 108 that are connected between the memory circuits 104A, 104B,104N and the system 106. The signals 108 may, for example, includeaddress signals, data signals, control signals, enable signals, clocksignals, reset signals, or any other signal used to operate orassociated with the memory circuits, system, or interface circuit(s),etc. In some optional embodiments, the signals may be those that: use adirect connection, use an indirect connection, use a dedicatedconnection, may be encoded across several connections, and/or may beotherwise encoded (e.g. time-multiplexed, etc.) across one or moreconnections.

In one aspect of the present embodiment, the interfaced signals 108 mayrepresent all of the signals that are connected between the memorycircuits 104A, 104B, 104N and the system 106. In other aspects, at leasta portion of signals 110 may use direct connections between the memorycircuits 104A, 104B, 104N and the system 106. The signals 110 may, forexample, include address signals, data signals, control signals, enablesignals, clock signals, reset signals, or any other signal used tooperate or associated with the memory circuits, system, or interfacecircuit(s), etc. In some optional embodiments, the signals may be thosethat: use a direct connection, use an indirect connection, use adedicated connection, may be encoded across several connections, and/ormay be otherwise encoded (e.g. time-multiplexed, etc.) across one ormore connections. Moreover, the number of interfaced signals 108 (e.g.vs. a number of the signals that use direct connections 110, etc.) mayvary such that the interfaced signals 108 may include at least amajority of the total number of signal connections between the memorycircuits 104A, 104B, 104N and the systems 106 (e.g. L>M, with L and M asshown in FIG. 1). In other embodiments, L may be less than or equal toM. In still other embodiments L and/or M may be zero.

In yet another embodiment, the interface circuit 102 and/or anycomponent of the system 106 may or may not be operable to communicatewith the memory circuits 104A, 104B, 104N for simulating at least onememory circuit. The memory circuits 104A, 104B, 104N shall hereafter bereferred to, where appropriate for clarification purposes, as the“physical” memory circuits or memory circuits, but are not limited to beso. Just by way of example, the physical memory circuits may include asingle physical memory circuit. Further, the at least one simulatedmemory circuit shall hereafter be referred to, where appropriate forclarification purposes, as the at least one “virtual” memory circuit. Ina similar fashion any property or aspect of such a physical memorycircuit shall be referred to, where appropriate for clarificationpurposes, as a physical aspect (e.g. physical bank, physical portion,physical timing parameter, etc.). Further, any property or aspect ofsuch a virtual memory circuit shall be referred to, where appropriatefor clarification purposes, as a virtual aspect (e.g. virtual bank,virtual portion, virtual timing parameter, etc.).

In the context of the present description, the term simulate orsimulation may refer to any simulating, emulating, transforming,disguising modifying, changing, altering, shaping, converting, etc., ofat least one aspect of the memory circuits. In different embodiments,such aspect may include, for example, a number, a signal, a capacity, aportion (e.g. bank, partition, etc.), an organization (e.g. bankorganization, etc.), a mapping (e.g. address mapping, etc.), a timing, alatency, a design parameter, a logical interface, a control system, aproperty, a behavior, and/or any other aspect, for that matter. Stillyet, in various embodiments, any of the previous aspects or any otheraspect, for that matter, may be power-related, meaning that suchpower-related aspect, at least in part, directly or indirectly affectspower.

In different embodiments, the simulation may be electrical in nature,logical in nature, protocol in nature, and/or performed in any otherdesired manner. For instance, in the context of electrical simulation, anumber of pins, wires, signals, etc. may be simulated. In the context oflogical simulation, a particular function or behavior may be simulated.In the context of protocol, a particular protocol (e.g. DDR3, etc.) maybe simulated. Further, in the context of protocol, the simulation mayeffect conversion between different protocols (e.g. DDR2 and DDR3) ormay effect conversion between different versions of the same protocol(e.g. conversion of 4-4-4 DDR2 to 6-6-6 DDR2).

In still additional exemplary embodiments, the aforementioned virtualaspect may be simulated (e.g. simulate a virtual aspect, the simulationof a virtual aspect, a simulated virtual aspect etc.). Further, in thecontext of the present description, the terms map, mapping, mapped, etc.refer to the link or connection from the physical aspects to the virtualaspects (e.g. map a physical aspect to a virtual aspect, mapping aphysical aspect to a virtual aspect, a physical aspect mapped to avirtual aspect etc.). It should be noted that any use of such mapping oranything equivalent thereto is deemed to fall within the scope of thepreviously defined simulate or simulation term.

More illustrative information will now be set forth regarding optionalfunctionality/architecture of different embodiments which may or may notbe implemented in the context of FIG. 1, per the desires of the user. Itshould be strongly noted that the following information is set forth forillustrative purposes and should not be construed as limiting in anymanner. For example, any of the following features may be optionallyincorporated with or without the other features described.

FIG. 2 shows an exemplary embodiment of an interface circuit that isoperable to interface memory circuits 202A-D and a system 204. In thisembodiment, the interface circuit includes a register 206 and a buffer208. Address and control signals 220 from the system 204 are connectedto the register 206, while data signals 230 from the system 204 areconnected to the buffer 208. The register 206 drives address and controlsignals 240 to the memory circuits 202A-D and optionally drives addressand control signals 250 to the buffer 208. Data signals 260 of thememory circuits 202A-D are connected to the buffer 208.

FIG. 3 shows an exemplary embodiment of an interface circuit that isoperable to interface memory circuits 302A-D and a system 304. In thisembodiment, the interface circuit includes a register 306 and a buffer308. Address and control signals 320 from the system 304 are connectedto the register 306, while data signals 330 from the system 304 areconnected to the buffer 308. The register 306 drives address and controlsignals 340 to the buffer 308, and optionally drives control signals 350to the memory circuits 302A-D. The buffer 308 drives address and controlsignals 360. Data signals 370 of the memory circuits 304A-D areconnected to the buffer 308.

FIG. 4 shows an exemplary embodiment of an interface circuit that isoperable to interface memory circuits 402A-D and a system 404. In thisembodiment, the interface circuit includes an advanced memory buffer(AMB) 406 and a buffer 408. Address, control, and data signals 420 fromthe system 404 are connected to the AMB 406. The AMB 406 drives addressand control signals 430 to the buffer 408 and optionally drives controlsignals 440 to the memory circuits 402A-D. The buffer 408 drives addressand control signals 450. Data signals 460 of the memory circuits 402A-Dare connected to the buffer 408. Data signals 470 of the buffer 408 areconnected to the AMB 406.

FIG. 5 shows an exemplary embodiment of an interface circuit that isoperable to interface memory circuits 502A-D and a system 504. In thisembodiment, the interface circuit includes an AMB 506, a register 508,and a buffer 510. Address, control, and data signals 520 from the system504 are connected to the AMB 506. The AMB 506 drives address and controlsignals 530 to the register 508. The register, in turn, drives addressand control signals 540 to the memory circuits 502A-D. It alsooptionally drives control signals 550 to the buffer 510. Data signals560 from the memory circuits 502A-D are connected to the buffer 510.Data signals 570 of the buffer 510 are connected to the AMB 506.

FIG. 6 shows an exemplary embodiment of an interface circuit that isoperable to interface memory circuits 602A-D and a system 604. In thisembodiment, the interface circuit includes an AMB 606 and a buffer 608.Address, control, and data signals 620 from the system 604 are connectedto the AMB 606. The AMB 606 drives address and control signals 630 tothe memory circuits 602A-D as well as control signals 640 to the buffer608. Data signals 650 from the memory circuits 602A-D are connected tothe buffer 608. Data signals 660 are connected between the buffer 608and the AMB 606.

In other embodiments, combinations of the above implementations shown inFIGS. 2-6 may be utilized. Just by way of example, one or more registers(register chip, address/control register chip, data register chip, JEDECregister, etc.) may be utilized in conjunction with one or more buffers(e.g. buffer chip, multiplexer/de-multiplexer chip, synchronousmultiplexer/de-multiplexer chip and/or other intelligent interfacecircuits) with one or more AMBs (e.g. AMB chip, etc.). In otherembodiments, these register(s), buffer(s), AMB(s) may be utilized aloneand/or integrated in groups and/or integrated with or without the memorycircuits.

The electrical connections between the buffer(s), the register(s), theAMB(s) and the memory circuits may be configured in any desired manner.In one optional embodiment, address, control (e.g. command, etc.), andclock signals may be common to all memory circuits (e.g. using onecommon bus). As another option, there may be multiple address, controland clock busses. As yet another option, there may be individualaddress, control and clock busses to each memory circuit. Similarly,data signals may be wired as one common bus, several busses or as anindividual bus to each memory circuit. Of course, it should be notedthat any combinations of such configurations may also be utilized. Forexample, the memory circuits may have one common address, control andclock bus with individual data busses. In another example, memorycircuits may have one, two (or more) address, control and clock bussesalong with one, two (or more) data busses. In still yet another example,the memory circuits may have one address, control and clock bus togetherwith two data busses (e.g. the number of address, control, clock anddata busses may be different, etc.). In addition, the memory circuitsmay have one common address, control and clock bus and one common databus. It should be noted that any other permutations and combinations ofsuch address, control, clock and data buses may be utilized.

These configurations may therefore allow for the host system to only bein contact with a load of the buffer(s), or register(s), or AMB(s) onthe memory bus. In this way, any electrical loading problems (e.g. badsignal integrity, improper signal timing, etc.) associated with thememory circuits may (but not necessarily) be prevented, in the contextof various optional embodiments.

Furthermore, there may be any number of memory circuits. Just by way ofexample, the interface circuit(s) may be connected to 1, 2, 4, 8 or morememory circuits. In alternate embodiments, to permit data integritystorage or for other reasons, the interface circuit(s) may be connectedto an odd number of memory circuits. Additionally, the memory circuitsmay be arranged in a single stack. Of course, however, the memorycircuits may also be arranged in a plurality of stacks or in any otherfashion.

In various embodiments where DRAM circuits are employed, such DRAM (e.g.DDR2 SDRAM) circuits may be composed of a plurality of portions (e.g.ranks, sub-ranks, banks, sub-banks, etc.) that may be capable ofperforming operations (e.g. precharge, active, read, write, refresh,etc.) in parallel (e.g. simultaneously, concurrently, overlapping,etc.). The JEDEC standards and specifications describe how DRAM (e.g.DDR2 SDRAM) circuits are composed and perform operations in response tocommands. Purely as an example, a 512 Mb DDR2 SDRAM circuit that meetsJEDEC specifications may be composed of four portions (e.g. banks, etc.)(each of which has 128 Mb of capacity) that are capable of performingoperations in parallel in response to commands. As another example, a 2Gb DDR2 SDRAM circuit that is compliant with JEDEC specifications may becomposed of eight banks (each of which has 256 Mb of capacity). Aportion (e.g. bank, etc.) of the DRAM circuit is said to be in theactive state after an activate command is issued to that portion. Aportion (e.g. bank, etc.) of the DRAM circuit is said to be in theprecharge state after a precharge command is issued to that portion.When at least one portion (e.g. bank, etc.) of the DRAM circuit is inthe active state, the entire DRAM circuit is said to be in the activestate. When all portions (e.g. banks, etc.) of the DRAM circuit are inprecharge state, the entire DRAM circuit is said to be in the prechargestate. A relative time period spent by the entire DRAM circuit inprecharge state with respect to the time period spent by the entire DRAMcircuit in active state during normal operation may be defined as theprecharge-to-active ratio.

DRAM circuits may also support a plurality of power management modes.Some of these modes may represent power saving modes. As an example,DDR2 SDRAMs may support four power saving modes. In particular, twoactive power down modes, precharge power down mode, and self-refreshmode may be supported, in one embodiment. A DRAM circuit may enter anactive power down mode if the DRAM circuit is in the active state whenit receives a power down command. A DRAM circuit may enter the prechargepower down mode if the DRAM circuit is in the precharge state when itreceives a power down command. A higher precharge-to-active ratio mayincrease the likelihood that a DRAM circuit may enter the prechargepower down mode rather than an active power down mode when the DRAMcircuit is the target of a power saving operation. In some types of DRAMcircuits, the precharge power down mode and the self refresh mode mayprovide greater power savings that the active power down modes.

In one embodiment, the system may be operable to perform a powermanagement operation on at least one of the memory circuits, andoptionally on the interface circuit, based on the state of the at leastone memory circuit. Such a power management operation may include, amongothers, a power saving operation. In the context of the presentdescription, the term power saving operation may refer to any operationthat results in at least some power savings.

In one such embodiment, the power saving operation may include applyinga power saving command to one or more memory circuits, and optionally tothe interface circuit, based on at least one state of one or more memorycircuits. Such power saving command may include, for example, initiatinga power down operation applied to one or more memory circuits, andoptionally to the interface circuit. Further, such state may depend onidentification of the current, past or predictable future status of oneor more memory circuits, a predetermined combination of commands to theone or more memory circuits, a predetermined pattern of commands to theone or more memory circuits, a predetermined absence of commands to theone or more memory circuits, any command(s) to the one or more memorycircuits, and/or any command(s) to one or more memory circuits otherthan the one or more memory circuits. Such commands may have occurred inthe past, might be occurring in the present, or may be predicted tooccur in the future. Future commands may be predicted since the system(e.g. memory controller, etc.) may be aware of future accesses to thememory circuits in advance of the execution of the commands by thememory circuits. In the context of the present description, suchcurrent, past, or predictable future status may refer to any property ofthe memory circuit that may be monitored, stored, and/or predicted.

For example, the system may identify at least one of a plurality ofmemory circuits that may not be accessed for some period of time. Suchstatus identification may involve determining whether a portion(s) (e.g.bank(s), etc.) is being accessed in at least one of the plurality ofmemory circuits. Of course, any other technique may be used that resultsin the identification of at least one of the memory circuits (orportion(s) thereof) that is not being accessed (e.g. in a non-accessedstate, etc.). In other embodiments, other such states may be detected oridentified and used for power management.

In response to the identification of a memory circuit that is in anon-accessed state, a power saving operation may be initiated inassociation with the memory circuit (or portion(s) thereof) that is inthe non-accessed state. In one optional embodiment, such power savingoperation may involve a power down operation (e.g. entry into an activepower down mode, entry into a precharge power down mode, etc.). As anoption, such power saving operation may be initiated utilizing (e.g. inresponse to, etc.) a power management signal including, but not limitedto a clock enable (CKE) signal, chip select (CS) signal, row addressstrobe (RAS), column address strobe (CAS), write enable (WE), andoptionally in combination with other signals and/or commands. In otherembodiments, use of a non-power management signal (e.g. controlsignal(s), address signal(s), data signal(s), command(s), etc.) issimilarly contemplated for initiating the power saving operation. Ofcourse, however, it should be noted that anything that results inmodification of the power behavior may be employed in the context of thepresent embodiment.

Since precharge power down mode may provide greater power savings thanactive power down mode, the system may, in yet another embodiment, beoperable to map the physical memory circuits to appear as at least onevirtual memory circuit with at least one aspect that is different fromthat of the physical memory circuits, resulting in a first behavior ofthe virtual memory circuits that is different from a second behavior ofthe physical memory circuits. As an option, the interface circuit may beoperable to aid or participate in the mapping of the physical memorycircuits such that they appear as at least one virtual memory circuit.

During use, and in accordance with one optional embodiment, the physicalmemory circuits may be mapped to appear as at least one virtual memorycircuit with at least one aspect that is different from that of thephysical memory circuits, resulting in a first behavior of the at leastone virtual memory circuits that is different from a second behavior ofone or more of the physical memory circuits. Such behavior may, in oneembodiment, include power behavior (e.g. a power consumption, currentconsumption, current waveform, any other aspect of power management orbehavior, etc.). Such power behavior simulation may effect or result ina reduction or other modification of average power consumption,reduction or other modification of peak power consumption or othermeasure of power consumption, reduction or other modification of peakcurrent consumption or other measure of current consumption, and/ormodification of other power behavior (e.g. parameters, metrics, etc.).

In one exemplary embodiment, the at least one aspect that is altered bythe simulation may be the precharge-to-active ratio of the physicalmemory circuits. In various embodiments, the alteration of such a ratiomay be fixed (e.g. constant, etc.) or may be variable (e.g. dynamic,etc.).

In one embodiment, a fixed alteration of this ratio may be accomplishedby a simulation that results in physical memory circuits appearing tohave fewer portions (e.g. banks, etc.) that may be capable of performingoperations in parallel. Purely as an example, a physical 1 Gb DDR2 SDRAMcircuit with eight physical banks may be mapped to a virtual 1 Gb DDR2SDRAM circuit with two virtual banks, by coalescing or combining fourphysical banks into one virtual bank. Such a simulation may increase theprecharge-to-active ratio of the virtual memory circuit since thevirtual memory circuit now has fewer portions (e.g. banks, etc.) thatmay be in use (e.g. in an active state, etc.) at any given time. Thus,there is higher likelihood that a power saving operation targeted atsuch a virtual memory circuit may result in that particular virtualmemory circuit entering precharge power down mode as opposed to enteringan active power down mode. Again as an example, a physical 1 Gb DDR2SDRAM circuit with eight physical banks may have a probability, g, thatall eight physical banks are in the precharge state at any given time.However, when the same physical 1 Gb DDR2 SDRAM circuit is mapped to avirtual 1 Gb DDR2 SDRAM circuit with two virtual banks, the virtual DDR2SDRAM circuit may have a probability, h, that both the virtual banks arein the precharge state at any given time. Under normal operatingconditions of the system, h may be greater than g. Thus, a power savingoperation directed at the aforementioned virtual 1 Gb DDR2 SDRAM circuitmay have a higher likelihood of placing the DDR2 SDRAM circuit in aprecharge power down mode as compared to a similar power savingoperation directed at the aforementioned physical 1 Gb DDR2 SDRAMcircuit.

A virtual memory circuit with fewer portions (e.g. banks, etc.) than aphysical memory circuit with equivalent capacity may not be compatiblewith certain industry standards (e.g. JEDEC standards). For example, theJEDEC Standard No. JESD 21-C for DDR2 SDRAM specifics a 1 Gb DRAMcircuit with eight banks. Thus, a 1 Gb virtual DRAM circuit with twovirtual banks may not be compliant with the JEDEC standard. So, inanother embodiment, a plurality of physical memory circuits, each havinga first number of physical portions (e.g. banks, etc.), may be mapped toat least one virtual memory circuit such that the at least one virtualmemory circuit complies with an industry standard, and such that eachphysical memory circuit that is part of the at least one virtual memorycircuit has a second number of portions (e.g. banks, etc.) that may becapable of performing operations in parallel, wherein the second numberof portions is different from the first number of portions. As anexample, four physical 1 Gb DDR2 SDRAM circuits (each with eightphysical banks) may be mapped to a single virtual 4 Gb DDR2 SDRAMcircuit with eight virtual banks, wherein the eight physical banks ineach physical 1 Gb DDR2 SDRAM circuit have been coalesced or combinedinto two virtual banks. As another example, four physical 1 Gb DDR2SDRAM circuits (each with eight physical banks) may be mapped to twovirtual 2 Gb DDR2 SDRAM circuits, each with eight virtual banks, whereinthe eight physical banks in each physical 1 Gb DDR2 SDRAM circuit havebeen coalesced or combined into four virtual banks. Strictly as anoption, the interface circuit may be operable to aid the system in themapping of the physical memory circuits.

FIG. 7 shows an example of four physical 1 Gb DDR2 SDRAM circuits 702A-Dthat are mapped by the system 706, and optionally with the aid orparticipation of interface circuit 704, to appear as a virtual 4 Gb DDR2SDRAM circuit 708. Each physical DRAM circuit 702A-D containing eightphysical banks 720 has been mapped to two virtual banks 730 of thevirtual 4 Gb DDR2 SDRAM circuit 708.

In this example, the simulation or mapping results in the memorycircuits having fewer portions (e.g. banks etc.) that may be capable ofperforming operations in parallel. For example, this simulation may bedone by mapping (e.g. coalescing or combining) a first number ofphysical portion(s) (e.g. banks, etc.) into a second number of virtualportion(s). If the second number is less than the first number, a memorycircuit may have fewer portions that may be in use at any given time.Thus, there may be a higher likelihood that a power saving operationtargeted at such a memory circuit may result in that particular memorycircuit consuming less power.

In another embodiment, a variable change in the precharge-to-activeratio may be accomplished by a simulation that results in the at leastone virtual memory circuit having at least one latency that is differentfrom that of the physical memory circuits. As an example, a physical 1Gb DDR2 SDRAM circuit with eight banks may be mapped by the system, andoptionally the interface circuit, to appear as a virtual 1 Gb DDR2 SDRAMcircuit with eight virtual banks having at least one latency that isdifferent from that of the physical DRAM circuits. The latency mayinclude one or more timing parameters such as tFAW, tRRD, tRP, tRCD,tRFC(MIN), etc.

In the context of various embodiments, tFAW is the 4-Bank activateperiod; tRRD is the ACTIVE bank a to ACTIVE bank b command timingparameter; tRP is the PRECHARGE command period; tRCD is theACTIVE-to-READ or WRITE delay; and tRFC(min) is the minimum value of theREFRESH to ACTIVE or REFRESH to REFRESH command interval.

In the context of one specific exemplary embodiment, these and otherDRAM timing parameters are defined in the JEDEC specifications (forexample JESD 21-C for DDR2 SDRAM and updates, corrections and errataavailable at the JEDEC website) as well as the DRAM manufacturerdatasheets (for example the MICRON datasheet for 1 Gb: ×4, ×8, ×16 DDR2SDRAM, example part number MT47H256M4, labeled PDF:09005aef821ae8bf/Source: 09005aef821aed36, 1 GbDDR2TOC.fm-Rev. K 9/06EN, and available at the MICRON website).

To further illustrate, the virtual DRAM circuit may be simulated to havea tRP(virtual) that is greater than the tRP(physical) of the physicalDRAM circuit. Such a simulation may thus increase the minimum latencybetween a precharge command and a subsequent activate command to aportion (e.g. bank, etc.) of the virtual DRAM circuit. As anotherexample, the virtual DRAM circuit may be simulated to have atRRD(virtual) that is greater than the tRRD(physical) of the physicalDRAM circuit. Such a simulation may thus increase the minimum latencybetween successive activate commands to various portions (e.g. banks,etc.) of the virtual DRAM circuit. Such simulations may increase theprecharge-to-active ratio of the memory circuit. Therefore, there ishigher likelihood that a memory circuit may enter precharge power downmode rather than an active power down mode when it is the target of apower saving operation. The system may optionally change the values ofone or more latencies of the at least one virtual memory circuit inresponse to present, past, or future commands to the memory circuits,the temperature of the memory circuits, etc. That is, the at least oneaspect of the virtual memory circuit may be changed dynamically.

Some memory buses (e.g. DDR, DDR2, etc.) may allow the use of 1T or 2Taddress timing (also known as 1T or 2T address clocking). The MICRONtechnical note TN-47-01, DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS(available at the MICRON website) explains the meaning and use of 1T and2T address timing as follows: “Further, the address bus can be clockedusing 1T or 2T clocking. With 1T, a new command can be issued on everyclock cycle 2T timing will hold the address and command bus valid fortwo clock cycles. This reduces the efficiency of the bus to one commandper two clocks, but it doubles the amount of setup and hold time. Thedata bus remains the same for all of the variations in the address bus.”

In an alternate embodiment, the system may change theprecharge-to-active ratio of the virtual memory circuit by changing from1T address timing to 2T address timing when sending addresses andcontrol signals to the interface circuit and/or the memory circuits.Since 2T address timing affects the latency between successive commandsto the memory circuits, the precharge-to-active ratio of a memorycircuit may be changed. Strictly as an option, the system maydynamically change between 1T and 2T address timing.

In one embodiment, the system may communicate a first number of powermanagement signals to the interface circuit to control the powerbehavior. The interface circuit may communicate a second number of powermanagement signals to at least a portion of the memory circuits. Invarious embodiments, the second number of power management signals maybe the same of different from the first number of power managementsignals. In still another embodiment, the second number of powermanagement signals may be utilized to perform power management of theportion(s) of the virtual or physical memory circuits in a manner thatis independent from each other and/or independent from the first numberof power management signals received from the system (which may or maynot also be utilized in a manner that is independent from each other).In alternate embodiments, the system may provide power managementsignals directly to the memory circuits. In the context of the presentdescription, such power management signal(s) may refer to any controlsignal (e.g. one or more address signals; one or more data signals; acombination of one or more control signals; a sequence of one or morecontrol signals; a signal associated with an active (or active)operation, precharge operation, write operation, read operation, a moderegister write operation, a mode register read operation, a refreshoperation, or other encoded or direct operation, command or controlsignal, etc.). The operation associated with a command may consist ofthe command itself and optionally, one or more necessary signals and/orbehavior.

In one embodiment, the power management signals received from the systemmay be individual signals supplied to a DIMM. The power managementsignals may include, for example, CKE and CS signals. These powermanagement signals may also be used in conjunction and/or combinationwith each other, and optionally, with other signals and commands thatare encoded using other signals (e.g. RAS, CAS, WE, address etc.) forexample. The JEDEC standards may be describe how commands directed tomemory circuits are to be encoded. As the number of memory circuits on aDIMM is increased, it is beneficial to increase the number of powermanagement signals so as to increase the flexibility of the system tomanage portion(s) of the memory circuits on a DIMM. In order to increasethe number of power management signals from the system withoutincreasing space and the difficulty of the motherboard routing, thepower management signals may take several forms. In some of these forms,the power management signals may be encoded, located, placed, ormultiplexed in various existing fields (e.g. data field, address field,etc.), signals (e.g. CKE signal, CD signal, etc.), and/or busses.

For example a signal may be a single wire; that is a single electricalpoint-to-point connection. In this case, the signal is un-encoded andnot bussed, multiplexed, or encoded. As another example, a commanddirected to a memory circuit may be encoded, for example, in an addresssignal, by setting a predefined number of bits in a predefined location(or field) on the address bus to a specific combination that uniquelyidentifies that command. In this case the command is said to be encodedon the address bus and located or placed in a certain position,location, or field. In another example, multiple bits of information maybe placed on multiple wires that form a bus. In yet another example, asignal that requires the transfer of two or more bits of information maybe time-multiplexed onto a single wire. For example, thetime-multiplexed sequence of 10 (a one followed by a zero) may be madeequivalent to two individual signals: a one and a zero. Such examples oftime-multiplexing are another form of encoding. Such various well-knownmethods of signaling, encoding (or lack thereof), bussing, andmultiplexing, etc. may be used in isolation or combination.

Thus, in one embodiment, the power management signals from the systemmay occupy currently unused connection pins on a DIMM (unused pins maybe specified by the JEDEC standards). In another embodiment, the powermanagement signals may use existing CKE and CS pins on a DIMM, accordingto the JEDEC standard, along with additional CKE and CD pins to enable,for example, power management of DIMM capacities that may not yet becurrently defined by the JEDEC standards.

In another embodiment the power management signals from the system maybe encoded in the CKE and CS signals. Thus, for example, the CKE signalmay be a bus, and the power management signals may be encoded on thatbus. In one example, a 3-bit wide bus comprising three signals on threeseparate wires: CKE[0], CKE[1], and CKE[2], may be decoded by theinterface circuit to produce eight separate CKE signals that comprisethe power management signals for the memory circuits.

In yet another embodiment, the power management signals from the systemmay be encoded in unused portions of existing fields. Thus, for example,certain commands may have portions of the fields set to X (also known asdon't care). In this case, the setting of such bit(s) to either a one orto a zero does not affect the command. The effectively unused bitposition in this field may thus be used to carry a power managementsignal. The power management signal may thus be encoded and located orplaced in a field in a bus, for example.

Further, the power management schemes described for the DRAM circuitsmay also be extended to the interface circuits. For example, the systemmay have or may infer information that a signal, bus, or otherconnection will not be used for a period of time. During this period oftime, the system may perform power management on the interface circuitor part(s) thereof. Such power management may, for example, use anintelligent signaling mechanism (e.g. encoded signals, sideband signals,etc.) between the system and interface circuits (e.g. register chips,buffer chips, AMB chips, etc.), and/or between interface circuits. Thesesignals may be used to power manage (e.g. power off circuits, turn offor reduce bias currents, switch off or gate clocks, reduce voltage orcurrent, etc) part(s) of the interface circuits (e.g. input receivercircuits, internal logic circuits, clock generation circuits, outputdriver circuits, termination circuits, etc.)

It should thus be clear that the power management schemes described hereare by way of specific examples for a particular technology, but thatthe methods and techniques are very general and may be applied to anymemory circuit technology and any system (e.g. memory controller, etc.)to achieve control over power behavior including, for example, therealization of power consumption savings and management of currentconsumption behavior.

While various embodiments have been described above, it should beunderstood that they have been presented by way of example only, and notlimitation. For example, any of the elements may employ any of thedesired functionality set forth hereinabove. Hence, as an option, aplurality of memory circuits may be mapped using simulation to appear asat least one virtual memory circuit, wherein a first number of portions(e.g. banks, etc.) in each physical memory circuit may be coalesced orcombined into a second number of virtual portions (e.g. banks, etc.),and the at least one virtual memory circuit may have at least onelatency that is different from the corresponding latency of the physicalmemory circuits. Of course, in various embodiments, the first and secondnumber of portions may include any one or more portions. Thus, thebreadth and scope of a preferred embodiment should not be limited by anyof the above-described exemplary embodiments, but should be defined onlyin accordance with the following claims and their equivalents.

1. A method, comprising: communicating with a plurality of physicalmemory circuits; and simulating at least one virtual memory circuit withat least one power-related aspect that is different from at least oneaspect of at least one of the physical memory circuits.
 2. The memory ofclaim 1, wherein the simulating is performed by an interface circuit. 3.The method of claim 2, wherein the interface circuit is selected fromthe group consisting of a buffer, a register, an advanced memory buffer(AMB), and a component positioned on at least one dual in-line memorymodule (DIMM).
 4. The method of claim 3, wherein the interface circuitincludes the buffer and is selected from the group consisting of abuffer chip, a data register chip, a multiplexer/de-multiplexer chip,and a synchronous multiplexer/de-multiplexer chip.
 5. The method ofclaim 3, wherein the interface circuit includes the register and isselected from the group consisting of an address register chip, acontrol register chip, and an address/control register chip.
 6. Themethod of claim 1, wherein the simulating is performed by a component ofa system.
 7. The method of claim 6, wherein the component of the systemincludes a memory controller.
 8. The method of claim 1, wherein the atleast one power-related aspect includes a timing.
 9. The method of claim1, wherein the at least one power-related aspect includes a relativeperiod of a first state of the physical memory circuits with respect toa period of a second state of the physical memory circuits.
 10. Themethod of claim 9, wherein the first state is a precharge state.
 11. Themethod of claim 9, wherein the second state is an active state.
 12. Themethod of claim 1, wherein the at least one power-related aspectincludes power behavior.
 13. The method of claim 12, wherein the atleast one power-related aspect includes a number of power managementsignals.
 14. The method of claim 12, wherein the at least onepower-related aspect includes a type of power management signals. 15.The method of claim 14, wherein the type of power management signals isselected from the group consisting of a time-multiplexed powermanagement signal, a bussed power management signal, an encoded powermanagement signal, and a unencoded power management signal.
 16. Themethod of claim 12, wherein the at least one power-related aspectincludes a placement of power management signals.
 17. The method ofclaim 16, wherein the placement of power management signals includesplacement of power management signals in at least one of an addressfield, a data field, at least one unused pin on a dual in-line memorymodule (DIMM), a clock enable signal, and a chip select signal.
 18. Anapparatus, comprising: a component of a system in communication with aplurality of physical memory circuits, the component of the systemoperable to communicate with the physical memory circuits and simulateat least one virtual memory circuit with at least one aspect that isdifferent from at least one aspect of at least one of the physicalmemory circuits.
 19. The apparatus of claim 18, wherein the component ofthe system includes a memory controller.
 20. The apparatus of claim 18,wherein the component of the system works in combination with aninterface circuit for simulating the at least one aspect.
 21. Theapparatus of claim 20, wherein the interface circuit interfaces at leastone of data signals and address signals.
 22. The apparatus of claim 20,wherein the component of the system simulates the at least one aspectutilizing a latency of the physical memory circuits.
 23. The apparatusof claim 18, wherein the at least one aspect includes a power-relatedaspect.
 24. The apparatus of claim 23, wherein the at least onepower-related aspect includes power management of an interface circuit.25. The apparatus of claim 23, wherein the at least one power-relatedaspect includes power management of at least one of a receiver circuitand a driver circuit of the interface circuit.
 26. The apparatus ofclaim 23, wherein the at least one power-related aspect is simulated byadjusting a parameter selected from the group consisting of a tFAWparameter, a tRRD parameter, a tRP parameter, a tRFC(min) parameter, anda tRCD parameter.
 27. The apparatus of claim 23, wherein the at leastone power-related aspect is simulated by switching between 1T and 2Tmodes.
 28. A method, comprising: communicating with at least onephysical memory circuit having a first number of portions; andsimulating at least one virtual memory circuit having a second number ofportions that is different from the first number of portions of the atleast one physical memory circuit.
 29. The method of claim 28, whereinthe second number is less than the first number.
 30. The method of claim19, wherein the second number of portions includes a single portion. 31.The method of claim 28, wherein the simulating results in a powersavings.
 32. A system, comprising: at least one physical memory circuithaving a first number of portions; and means for simulating at least onevirtual memory circuit having a second number of portions that isdifferent from the first number of portions of the at least one physicalmemory circuit.
 33. A method, comprising: communicating with a pluralityof physical memory circuits; and simulating at least one virtual memorycircuit with at least one aspect that is different from at least oneaspect of at least one of the physical memory circuits; wherein the atleast aspect is selected from the group consisting of a signal, aportion, a partition, an organization, a mapping, a timing, and alatency.